产品

Product

说明

Description

前提注释

Prerequisite Notes

备注

TetraMAX IddQ Test

Verifies IDDQ compliance for TetraMAX ATPG and functional vectors.

VCS or IEEE-compliant Verilog simulator

TetraMAX DSMTest

Enables DSM fault models: transition, path delay, bridging and dynamic bridging. Also enables power-aware and timing-aware features.

TetraMAX ATPG

TetraMAX ATPG

Provides manufacturing test patterns for scan designs. Includes failure diagnostics for defect isolation, and fault simulation for functional vectors. Does not provide DFT synthesis.

DFTMAX for adaptive scan. No prerequisite for standard scan.

Formality

Fast, easy to use RTL-gate and gate-gate equivalence checking for DC Ultra/DC Grapical. Incudes low power support and multi-core

Internal Comments: Combined with DC Ultra/DC Graphical, provides the highest QoR that is verifiable.

Pioneer NTB with Vera

Standalone SystemVerilog and OpenVera testbench automation tool. It allows users to create SystemVerilog or OpenVera testbench that can be run with VCS and 3rd party simulators. Developer Kit includes compilation, runtime and debug.

Core Builder

Guides the IP designer through the process of capturing the necessary design files, information and designer knowledge necessary to deliver high quality, easily reusable cores supporting IP-XACT.

DC Ultra

RTL Synthesis solution for all designs. Delivers best-in-class timing, area and power results. Includes Topographical Technology to boost productivity.

HDL Compiler Verilog and DesignWare Library or VHDL Compiler and DesignWare Library。

HDL Compiler Verilog

Front-end for Design Compiler, Reads in Verilog or SystemVerilog HDL description

DC Expert or DC Ultra

Library Compiler

Prepares libraries from Open-Source Liberty format with timing, area, power, test and function information for use in Galaxy Flow (DC family, PT family, ICC).

Module Compiler

Datapath synthesis tool.

Power Compiler

Complete power synthesis and optimization solution. Provides optimization for multi-voltage, multi-Vt, advanced clock-gating and power management cell insertion via UPF. Enables UPF for DC Ultra.

DC Expert or DC Ultra for power optimization. Internal Comments: Power Compiler is a requirement for UPF usage in DC Ultra.

VHDL Compiler

Front-end for Design Compiler, Reads in VHDL description.

DC Expert or DC Ultra

DesignWare Library

Includes key infrastructure IP for SoC design & verification datapath, building block IP, Foundry Libraries, AMBA OCB, Peripherals ( DMA, UART, I2C), Microcontrollers (8051, 6811), Memory IP & Verification IP.

DesignWare Developer

Tool for Generation of User Defined DesignWare components.

Design Vision

Graphical User Interface(GUI) for Design Compiler, enables intuitive and easy visual analysis of designs.

DC Expert or DC Ultra。

PrimeTime SI

Gate-level static timing analysis (STA) and signoff tool, including signal integrity (SI) noise analysis and advanced on chip variation handling. Recommended base product configuration for 90nm and below process technologies.

Internal Comments: At 90-nm and below, SI and noise analysis are recommended for signoff.

VCS Verification Library

Combines the DesignWare protocol-based verification suites including VMM support into a package that is more cost effective for multi-protocol simulations or for multi-project customers. Supports Verilog and VHDL on all simulators.

Provides support for VMM on VCS. Supports Verilog and VHDL on all simulators. Customers using this product with simulators other than VCSor VCS-MX will need to install Vera.

VCS MX

Verilog, VHDL, SystemVerilog and SystemC simulator with native testbench, plus support for VMM/UVM/OVM methodologies and Discovery VIP. Includes built-in debugger for design, testbench, assertions, and coverage visualization.

CoreAssembler

Tool for generating connectivity netlists for Subsyystems, full Soc as well as test benches supporting SystemVeriliog Methodolgies

MVSIM

MVSIM provides comprehensive verification coverage for low-power designs using advanced power management techniques. MVSIM enables accurate RTL or gate-level Voltage-Aware simulation natively in VCS (PLI mode continues to be available).

MVRC

MVRC provides comprehensive static checking for low-power designs using advanced power management techniques. MVRC performs architectural and structural checks for correct implementation of power intent from RTL to Gate level.

ESP-CV

ESP-CV performs Verilog vs. SPICE netlist equivalence checking for functional verification of full-custom memories, datapath blocks and IO cells.

Formality ESP

Formality ESP performs Verilog vs. SPICE netlist equivalence checking for functional verification of cell libraries and simple embedded SRAMs and register files. This tool is an add-on to Formality.

Formality

DFTMAX

Provides compression, scan, and boundary synthesis. Also enables TetraMAX ATPG for compression.

DC Expert or DC Ultra.

NanoTime

Next generation transistor-level static timing analysis solution for custom design.

PrimeTime PX Add-On

Gate-level power analysis option; includes average power, peak power and cycle-based power analysis. Support for vector-free and simulation-based stimulus for analysis.

PrimeTime/PrimeTime SI. For optional waveform viewing, several alternatives are available: CosmosScope or Custom WaveView. Another alternative is to OEM nWave

NanoTime Ultra Add-On

Provides advanced technologies, such as SI.

NanoTime

Custom Explorer Ultra

Netlist-based mixed-signal verification and debug environment.

PrimeTime GCA

Timing constraint analysis and debug add-on to PrimeTime - Provides fast, efficient constraint analysis and debug correlated to PrimeTime static timing analysis. Includes version to version and block to top hierarchical constraint comparison capabilities.

PrimeTime or PrimeTime SI

DesignWare TLM Library

Licenses to run TLM models respresenting specific Synopsys DesignWare interface IP

产品

Product

说明

Description

前提注释

Prerequisite Notes

备注

Library Compiler

Prepares libraries from Open-Source Liberty format with timing, area, power, test and function information for use in Galaxy Flow (DC family, PT family, ICC).

PrimeTime SI

Gate-level static timing analysis (STA) and signoff tool, including signal integrity (SI) noise analysis and advanced on chip variation handling. Recommended base product configuration for 90nm and below process technologies.

Internal Comments: At 90-nm and below, SI and noise analysis are recommended for signoff.

BDC for NanoSim

BDC (Block Delay Calculator) add-on for NanoSim.

NanoSim

IC WorkBench Edit/View Plus

Fast layout viewer and editor, supporting GDSII and OASIS formats.

Internal Comments: ICWBEV+ is required for large-area GDSII/OASIS database viewing within Sentaurus TCAD, Sentaurus Lithography, and ICV

ESP-CV

ESP-CV performs Verilog vs. SPICE netlist equivalence checking for functional verification of full-custom memories, datapath blocks and IO cells.

HSPICE RF

Add-on package to HSPICE (4660-0) for RF simulation.

HSPICE

IC Compiler

Single convergent netlist to post route solution for 28nm and older technologies. Takes as input gate level netlist, detailed floorplan, timing constraints, physical and timing libraries, and foundry process data and generates GDSII output.

PrimeRail

Advanced gate-level IR-drop and electromigration analysis tool; includes static and dynamic full-chip analysis capability.

Internal Comments: Companion product for IC Compiler based flows

NanoTime

Next generation transistor-level static timing analysis solution for custom design.

CustomSim CircuitCheck op.

Static and dynamic functions for parametric checks, ERC, logic & timing diagnostics, signal integrity and leakage checks.

CustomSim or CustomSim-MS or CustomSim-SC

CustomSim Cadence ADE I/F op.

Integration into Cadence Analog Design Environment

CustomSim or CustomSim-MS or CustomSim-SC

CustomSim Digital Co-Sim op.

Enables Co-Simulation with VCS and 3rd Party Digital Simulators

CustomSim or CustomSim-MS or CustomSim-SC

IC Compiler MR 8:8 Node Dist Rt. Op

Add-on to IC Compiler, IC Compiler -XP, and IC Compiler-PC for distributed routing for any number of nodes with the classic router. Not required or supported with Zroute. Zroute is the default router in ICC, ICC-PC and ICC-DP

IC Compiler or IC Compiler-PC or IC Compiler-XP

PrimeTime PX Add-On

Gate-level power analysis option; includes average power, peak power and cycle-based power analysis. Support for vector-free and simulation-based stimulus for analysis.

PrimeTime or PrimeTime SI. optional waveform viewing:  CosmosScope or Custom WaveView.

NanoTime Ultra Add-On

Provides advanced technologies, such as SI.

NanoTime

Analysis Command Environment

Tcl and Perl-driven high-level functional APIs for application-specific customization.

Custom WaveView or CustomExplorer

SX-CDS Link

SX-CDS Link framework integrations offer direct schematic-to-viewer cross probing capabilities from Cadence Design Systems Virtuoso Platform products.

Custom WaveView or CustomExplorer

SX-DAIC Link

SX-DAIC Link framework integrations offer direct schematic-to-viewer cross probing capabilities from Mentor Graphics Design Architect.

Custom WaveView or CustomExplorer

SX-ADP Link

SX-ADP Link framework integrations offer direct schematic-to-viewer cross probing capabilities from Silicon Canvas ADP.

Custom WaveView or CustomExplorer

SX-JEDAT Link

SX-JEDAT Link framework integrations offer direct schematic-to-viewer cross probing capabilities from JEDAT SX.

Custom WaveView or CustomExplorer

SX-CDS ENS

SX-CDS ENS Link framework integrations offer direct extracted netlist-to-viewer cross probing capabilities from Cadence Design Systems Virtuoso Platform products.

Custom WaveView or CustomExplorer

SX-DATA options

WaveView Analyzer / Spice Explorer support for oscilloscope waveform data analysis.

Custom WaveView or CustomExplorer

HSPICE

High accuracy analog circuit simulator.

IC Compiler Design Planning

Hierarchical design planning for feasibility analysis and detailed floorplanning and is fully integrated with IC Compiler.

CustomExplorer Ultra

Netlist-based mixed-signal verification and debug environment.

Custom Designer SE

Next-Generation Custom Schematic Editor

Custom Designer LE

Next-Generation Custom Layout Editor

CustomSim

Shared license fastspice product for XA, HSIM and NanoSim

CustomSim-FT

Capacity limited XA for Fast Transient simulation using HSPICE netlist of up to 30K transistors.

Requires 4 HSPICE licenses.

CosmosScope

Waveform viewer and postprocessing for analog and mixed-signal waveforms. Supports HSPICE, Nanosim, VCS and Saber.

IC Validator /Hercules DP

Enables the customer to use one additional CPU for any multi-processing task with Hercules or IC Validator

IC Validator/Hercules, or IC Validator /Hercules LVS, or IC Validator/Hercules DRC

IC Validator /Hercules

This is equivalent to a combination of IC Validator/Hercules LVS, plus IC Validator/Hercules DRC, plus one IC Validator/Hercules DP. It allows a DRC and an LVS job to run concurrently. Either job can use the DP license.

 IC WorkBench Edit/View Plus with this license. Free upgrades from: Hercules HDRC　 Hercules HLVS -OR- Hercules HDRC w/Herc Basic Hercules HLVS w/Herc Basic

Custom Designer LE Plus Add-On

Custom Designer SDL significantly improves layout productivity be managing the complex job of synchronizing the schematic of a design and its layout.

Custom Designer LE

PrimeTime GCA

Timing constraint analysis and debug add-on to PrimeTime - Provides fast, efficient constraint analysis and debug correlated to PrimeTime static timing analysis. Includes version to version and block to top hierarchical constraint comparison capabilities.

PrimeTime or PrimeTime SI.

StarRC Ultra

Parasitic Extraction for advanced gate-level and transistor-level design and analysis, including 20nm DPT with multi-value SPEF support, FinFET, 3D-IC, multi-corner and statistical signoff extraction.

Galaxy-3D  Internal Comments: Prerequisite required by StarRC Ultra 3D-IC feature